1. Field of the Invention
The present invention relates generally to a timing error detector. In particular, it relates to the design of an asynchronous counter based timing error detector.
2. Description of the Background Art
The phase-locked loop is a key building block as it can generate a well-defined frequency. The prior art uses a phase-frequency detector and a charge pump to extract the timing relationship between a reference clock and an oscillator clock. The nature of this approach is analog that is inferior in deep submicron technology. An asynchronous counter based timing error detector is presented in this work that utilizes an all-digital implementation to replace the conventional analog-intensive phase-frequency detector and charge pump.